Mastering AMBA CHI: Part 1—Architectural Foundations

The transition from AXI (Advanced eXtensible Interface) and ACE (AXI Coherency Extensions) to CHI (Coherent Hub Interface) marks a fundamental shift in how complex System-on-Chips (SoCs) are designed. As core counts escalated and heterogeneous compute—integrating CPUs, GPUs, and NPUs on a single die—became standard, the limitations of traditional interconnects became apparent.

This first installment of the AMBA CHI series explores the architectural imperatives that drove the development of CHI, the structure of its layered protocol, and the taxonomy of nodes that constitute a CHI network.

The Scalability Wall: Moving Beyond ACE

ACE served the industry well for small to medium-sized clusters, typically involving a handful of coherent masters. However, ACE relies heavily on broadcast snooping. When a master initiates a coherent transaction, snoop requests must be broadcast to all other coherent caches in the system.

In a massive SoC with dozens of compute clusters, broadcast snooping introduces prohibitive overhead:

1. Snoop Filter Thrashing: A central snoop filter can bottleneck performance as it struggles to keep up with broadcast traffic.
2. Wire Routing Congestion: The sheer number of physical wires required to connect all masters to an interconnect point creates routing nightmares during physical layout.
3. Power Consumption: Waking up idle caches merely to respond to a snoop miss consumes significant dynamic power.

CHI addresses these limitations by shifting from a crossbar-centric, broadcast-heavy paradigm to a packet-based, network-on-chip (NoC) architecture utilizing a centralized directory structure at the Home Node.

The CHI Layering Model

Much like Ethernet or PCIe, CHI employs a layered architecture. This separation of concerns allows physical transport implementation to evolve independently of the logical coherency protocol.

Layer	Responsibility	Details
Protocol Layer	Coherency state machines, transaction flows	Defines states (e.g., MOESI), transaction types (e.g., ReadShared, WriteBack), and logical responses.
Network Layer	Routing and packetization	Handles the routing of messages between nodes using SrcID (Source ID) and TgtID (Target ID).
Link Layer	Flow control and physical transmission	Manages flit transmission between adjacent nodes (routers) using a credit-based flow control mechanism.

Flits and Phits

Data in CHI is transmitted as discrete units called flits (flow control units). A flit is the smallest unit of information recognized by the Link layer for flow control. The physical width of the link determines the phit (physical unit), which is the number of bits transmitted in a single clock cycle. If a link is 256 bits wide and a data flit requires 512 bits, transmitting one flit takes two phits.

Node Taxonomy in CHI

A CHI system is composed of several node types, each with specific roles in the coherency and memory access domains.

Request Nodes (RN)

Request Nodes are the masters of the system. They generate protocol transactions.

• RN-F (Fully Coherent Request Node): Contains a hardware-managed coherent cache (e.g., an Arm Cortex-A CPU cluster). It responds to snoop requests and maintains cache line states.
• RN-D (DVM Request Node): Capable of receiving Distributed Virtual Memory (DVM) messages, primarily used by MMUs or SMMUs to handle TLB invalidations.
• RN-I (I/O Request Node): An I/O master without a coherent cache (e.g., a PCIe root complex or DMA controller). It can read or write coherent memory but does not cache it.

Home Nodes (HN)

Home Nodes act as the orchestrators of coherency and the point of serialization for transactions targeting a specific address range.

• HN-F (Fully Coherent Home Node): The heart of the CHI system. It manages the directory or snoop filter, serializes requests to the same address, generates snoops to RN-Fs, and interfaces with the downstream memory controller.
• HN-I (I/O Home Node): Manages requests to non-coherent address space, such as memory-mapped I/O peripherals.

Slave Nodes (SN)

Slave nodes are the ultimate endpoints for data.

• SN-F (Slave Node - Flash/Memory): Typically the memory controller (e.g., DDR/HBM PHY). It receives read/write requests from the HN-F.
• SN-I (Slave Node - I/O): The endpoint for peripheral access, receiving requests from the HN-I.

The Four CHI Channels

Communication between nodes occurs over four distinct physical or logical channels. Unlike AXI, where Address and Data are tightly coupled in phase, CHI completely decouples them, allowing data to be returned out-of-order or via different physical routes.

1. REQ (Request): Initiates a transaction (e.g., an RN-F requesting a read or write). Carries the transaction type, address, and attributes.
2. SNP (Snoop): Generated by the HN-F and sent to RN-Fs to query or invalidate cache lines.
3. RSP (Response): Carries completion acknowledgments, snoop responses, and credit returns. Crucially, it does not carry payload data.
4. DAT (Data): Dedicated exclusively to payload data. Data can be sent from SN-F to RN-F, from RN-F to HN-F (writeback), or directly from one RN-F to another RN-F (Direct Data Transfer).

By fully packetizing these channels, CHI allows topologies to range from simple crossbars to complex ring and 2D mesh networks, scaling to hundreds of nodes while maintaining strict ordering and coherency guarantees. In the next part, we will examine the coherency protocol itself and how the Home Node orchestrates state transitions.