Mastering AMBA CHI: Part 5—Advanced Operations

The baseline AMBA CHI protocol excels at moving coherent data efficiently across a massive topology. However, modern System-on-Chips (SoCs)—featuring tightly integrated Neural Processing Units (NPUs), high-throughput network interfaces, and massive core counts—require more than just basic read and write operations.

In this final installment, we explore the advanced features of CHI designed specifically to reduce software overhead, accelerate heterogenous workloads, and manage system-wide virtualization.

Atomic Operations: Offloading Synchronization

In older architectures (like AXI), atomic operations were typically implemented using Exclusive Accesses (Load-Exclusive and Store-Exclusive pairs). This required pulling a cache line into the core’s local L1, locking the monitor, performing the math, and writing it back. Under high contention (e.g., many cores competing for a spinlock), this resulted in immense network traffic and cache line bouncing.

CHI introduces hardware-level Atomic transactions, moving the computation closer to the data.

At-Memory and In-Cache Atomics

Instead of pulling the data to the CPU, the CPU sends an Atomic transaction (containing the address, the operand, and the logical operation) to the interconnect.

• In-Cache Atomics: The HN-F orchestrates the operation. If the data resides in a peer RN-F’s cache, the HN-F can execute the atomic operation on the data as it passes through the Home Node, or instruct the target node to execute it.
• At-Memory Atomics: The transaction is forwarded all the way to the memory controller (SN-F). The SN-F executes the logical operation (e.g., an AtomicAdd or AtomicCompare) directly in the memory controller’s logic before committing the result to DRAM.

This drastically reduces interconnect traffic. A highly contended variable no longer bounces between L1 caches; instead, simple atomic arithmetic packets are routed directly to the point of serialization.

Cache Stashing: Producer-Consumer Optimization

A common bottleneck in heterogeneous systems is the producer-consumer pattern. For instance, a PCIe Network Interface Controller (NIC) receives an Ethernet frame and writes the payload to main memory. A CPU core must then read that data from memory to process the packet, incurring significant latency.

CHI addresses this with Cache Stashing.

Stashing allows an initiator (like an I/O device or an NPU) to proactively push data directly into the local cache of a specific CPU core.

1. The NIC initiates a WriteUniquePtlStash transaction.
2. Alongside the data, the NIC includes the target CPU’s Node ID (StashNID).
3. The interconnect routes the write to the Home Node, which updates memory, but also forwards the data directly into the L2 or L3 cache of the targeted CPU.
4. When the CPU receives the interrupt to process the packet, the data is already waiting in its low-latency cache, bypassing the DRAM read penalty.

Distributed Virtual Memory (DVM)

Modern SoCs utilize Memory Management Units (MMUs) at the CPUs and System MMUs (SMMUs) in front of accelerators to provide process isolation and virtual memory. When an OS modifies page tables (e.g., unmapping a page of memory), the translation lookaside buffers (TLBs) across the entire system must be synchronized and invalidated.

CHI standardizes this via DVM (Distributed Virtual Memory) messages.

Instead of requiring software to manually interrupt every core to flush TLBs, the OS executes a localized TLB invalidate instruction. The hardware translates this into a DVM transaction on the interconnect.

• The originating Request Node sends a DVMOp transaction to a specialized DVM Home Node.
• The Home Node broadcasts this operation to all nodes in the system registered as RN-Ds (DVM Request Nodes).
• The peer nodes perform the local TLB invalidation and send a CompAck to the Home Node.
• The originating CPU waits until the hardware signals that all system TLBs have been synchronized before proceeding.

Conclusion

The AMBA CHI specification is a massive, complex protocol designed to solve the hardest problems in SoC scaling. By abandoning broadcast snooping in favor of a packetized, directory-based, and highly decoupled architecture, CHI provides the bandwidth and latency guarantees required for server-grade CPUs and advanced AI accelerators. From credit-based flow control preventing deadlocks to hardware atomics eliminating software bottlenecks, CHI is the foundational nervous system of the modern high-performance silicon era.